1. Technical Field:
The present invention relates in general to the allocation of resources during the execution of instructions in a microprocessor, and in particular the present invention relates to the early deallocation of resources dedicated to a serialized load/store multiple operation to allow simultaneous execution of additional instructions.
2. Description of the Related Art:
Multi-register load/store instructions require complete serialization since these instructions modify or use up to all general purpose registers (usually 32) contained within a microprocessor. In the PowerPC.TM. line of microprocessors produced by International Business Machines, Inc., integer load/store multiple instructions are accommodated, which move blocks of data to and from the microprocessors general purpose registers (GPRs). The multi-register instructions provided are the Load Multiple Word (lmw) and the Store Multiple Word (stmw) instructions.
In the prior art, because such multi-register load/store instructions may modify or use up to all the general purpose registers in the system, later instructions in the instruction sequence are held in the instruction buffer until the multi-register instruction is complete. Therefore, it was assumed that multi-register instructions force complete serialization of these instructions in the instruction stream. To implement such a serialization in the prior art, the multi-register instructions are allocated all of the required general purpose registers until the instruction completed. Such a system substantially restricts performance by holding up the instruction pipeline until the multi-register instruction is completed.
What is needed is a mechanism to allow resources to be deallocated from the multi-register instructions as those instructions are executed and the resources become available to allow subsequent instructions to begin execution simultaneously with the executing multi-register instruction. Such a mechanism would substantially improve the performance of a microprocessor having a superscalar design by allowing instructions that utilize multiple registers to be executed in parallel with subsequent instructions that utilize the GPRs.